iw4520 b description the iw4520 b dua l bi nar y up - c oun t er cons i s t s t wo i den ti ca l , i n te rna ll y s y nchronous 4 - s t ag e coun t ers. the coun t er s t ages are d - ty pe f li p - f l ops hav i ng i n te rchang eable clock and enable lines for i n cre m e n ti ng o n eit h e r t h e pos iti v e - go i ng or n e g ati v e - go i ng tra n siti on . for s i ng l e - un it opera ti on t he ena b le i nput i s m ai n tai ned h i gh and the counter advances on each positi v e - going transition of the clock . the coun t ers are c l eared by h i gh le ve l s on t he i r re set li nes. the coun t er can be cascaded i n t he r i pp l e m ode b y connec ti ng q4 t o t he enab le i npu t of t he subsequent coun t er wh ile t he cl o c k i nput of t h e latter is h el d l o w. features ? operati ng volta g e ra ng e: 3.0 to 18 v 16 16 ? ? ma x i m u m i n p u t c u rre n t of 1 u a at 18 v o v er fu ll pac k a g e - t e m pera t u re range ; 100 n a a t 18 v a n d 25 c ? ? ? noi s e m ar g i n (o v er fu ll pac k a g e te m perat u re ra ng e): 1.0 v m i n @ 5.0 v s u pp l y 2.0 v m i n @ 10.0 v s u pp l y 2.5 v m i n @ 15.0 v s u pp l y dip - 16 sop - 16 package pin assignment logic diagram clock a 1 enable a 2 r 3 4 5 6 q1a q2a q3a q4a clock a enable a q1 a q2 a q3 a q4 a 1 2 3 4 5 6 7 16 15 14 13 12 11 10 v cc reset b q4 b q3 b q2 b q1 b enable b reset a 7 gnd 8 9 clock b clock b 9 11 12 q1 b q2 b function table inpu t s ou t pu t s clock e nable reset m ode enable reset b 10 b 15 pi n 16 = v cc pi n 8 = gnd r 13 14 q3 b q4 b h l incre m en t c oun t er l l incre m en t c oun t er x l no c hange x l no c hange l l no c hange h l no c hange x x h t hr u q 4 q = 1 l x = don ' t care 1 beijing estek electronics co.,ltd
iw4520 b absolute maximum ratings s y m bol para m ete r va l ue un i t v cc dc supp ly vo lta ge (referenced t o gnd) - 0.5 t o +20 v v in dc inpu t vo lta ge (referenced t o gnd) - 0.5 t o v +0.5 v v out dc output voltage (referenced to gnd) c c - 0.5 to v +0.5 v i in d c inpu t c urren t , per p i n 10 ma p d p o wer dissi p ati on i n still air, plastic dip+ soic package+ 750 500 mw p d power d i ss i pa ti on per ou t pu t trans i s t or 100 m w ts t g s t orage te m pera t ure - 65 t o +150 c t l lead te m pera t ure, 1 mm fro m ca se for 10 seconds (plastic dip or soic package) 260 c ma x i m u m rati ngs are t hose va l ues be y ond wh ic h da m a ge t o t he dev i ce m ay occur. functional operation should be restricted to the rec o mm e nded operating conditions. +dera ti ng - p l as tic dip : - 10 m w/ c fro m 65 t o 125 c soic package: : - 7 m w/ c fro m 65 t o 125 c recommended operating conditions symbo l parameter mi n max unit v c c dc supply voltage (referenced to gnd ) 3.0 18 v v i n , v ou t dc input voltage, output voltage (referenced to gnd ) 0 v c c v t a operating temperature, all package types - 55 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high - impedance circuit. for proper operation, v i n and v ou t should be constrained to the range gnd ( v i n or v ou t ) ? v c c . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc unused outputs must be left open. beijing estek electronics co.,ltd 2
iw4520 b dc ele ctr ic a l c h ara ct e r i st ic s (voltages referenced to gnd) v c c guaranteed limit symbo l parameter test conditions v ? - 5 5 c 2 5 c ? 125 c unit v i h minimum high - level input voltage v i l maximum low - level input voltage v ou t =0.5 v or v c c - 0.5 v v ou t =1.0 v or v c c - 1.0 v v ou t =1.5 v or v c c - 1.5 v v ou t =0.5 v or v c c - 0.5 v v ou t =1.0 v or v c c - 1.0 v v ou t =1.5 v or v c c - 1.5 v 5.0 10 15 5.0 10 15 3.5 7 11 1.5 3 4 3.5 7 11 1.5 3 4 3.5 7 11 1.5 3 4 v v v o h minimum high - level output voltage v i n =gnd or v c c 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v o l maximum low - level output voltage v i n =gnd or v c c 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i i n maximum input leakage current i c c maximum quiescent supply current (per package) v i n = gnd or v c c 18 v i n = gnd or v c c 5.0 10 15 20 + - 0.1 5 10 20 100 + - 0.1 5 10 20 100 + - 1.0 150 300 600 3000 u a u a i o l minimum output low (sink) current i o h minimum output high (source) curren t v i n = gnd or v cc v ol =0.4 v v ol =0.5 v v ol =1.5 v v i n = gnd or v cc v o h =4.6 v v o h =2.5 v v o h =9.5 v v o h =13.5 v 5.0 10 15 5.0 5.0 10 15 0.64 1.6 4.2 - 0.64 ? 2.0 ? 1.8 ? 4.2 0.51 1.3 3.4 - 0.51 ? 1.6 ? 1.3 ? 3.4 0.36 0.9 2.4 - 0.36 ? 1.15 ? 0.9 ? 2.4 ma ma 3 beijing estek electronics co.,ltd
iw4520 b ac ele ctr ic a l c h ara ct e r i st ic s (c l =50pf, r l =200 k ? , input t r = t f =20 ns) v guaranteed li m i t sy m bol para m e ter v - 55 c 25 c 125 c unit f m a x ma x i m u m cl ockfrequenc y , (f i gure 1) 5.0 10 15 1.5 3 4 1.5 3 4 0.75 1.5 2 m h z t ph l , t pl h ma x i m u m propaga ti on de lay , cl ock or enab l e t o ou t pu t (f i gures 1,3) t ph l ma x i m u m propaga ti on de lay , re se t t o ou t put (f i gure 2) t thl , t tlh ma x i m u m ou t pu t trans iti on t i m e , an y ou t put 5.0 10 15 5.0 10 15 5.0 10 15 560 230 160 650 225 170 200 100 80 560 230 160 650 225 170 200 100 80 1120 460 320 1300 450 340 400 200 160 ns ns ns c in ma x i m u m inpu t ca pac ita nce - 7.5 pf timing requirements (c l =50pf, r l =200 k ? , input t r = t f =20 ns) v guaranteed li m i t sy m bol para m e ter v - 55 c 25 c 125 c unit t w t w t w mi n i m u m pu l se w i d t h, cl ock (f i gure 1) 5.0 10 15 mi n i m u m pu l se w i d t h, re se t (f i gure 2) 5.0 10 15 mi n i m u m pu l se w i d t h, enab le (f i gure 3) 5.0 10 15 200 100 70 250 110 80 400 200 140 200 100 70 250 110 80 400 200 140 400 200 140 500 220 160 800 400 280 ns ns ns t r , t ma x i m u m inpu t ri se and fa ll t i m e s (f i gure 1) 5.0 10 15 15 5 5 15 5 5 15 5 5 s 4 beijing estek electronics co.,ltd
iw4520 b tr tf clock 90% 50% 10% tw 1/fmax vcc gnd reset 50% t phl tw vcc gnd 50% 90% t plh t phl vcc output 50% vcc gnd output 10% gnd t t f i gure 1. s wi tch i ng waveforms f i gure 2. s wi tch i ng waveforms enable 50% tw vcc gnd output t plh t phl 50% vcc gnd timing diagram clock enable 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 q1 q2 q3 q4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 beijing estek electronics co.,ltd
iw4520 b expanded logic diagram (1/2 of the device) q1 q2 q3 q4 d q q d q d q d q r c q c q c q reset r r r enable address : 6a06 -- 6a07 rm 6a07,changyin office building ,no.88,yong ding road,hai dian district ,beijing postalcode:100039 tel: 86 - 010 - 58895780 / 81 / 82 / 83 / 84 fax : 010 - 58895793 http://www.estek.com.cn email:sales@estek.com.cn rev no:01 - 060837 6 beijing estek electronics co.,ltd
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